diff options
| author | Peter Griffin <[email protected]> | 2024-04-26 13:20:02 +0100 |
|---|---|---|
| committer | Martin K. Petersen <[email protected]> | 2024-05-06 21:34:37 -0400 |
| commit | c9deb9a4f574b49bfd00be88aba470659d2db671 (patch) | |
| tree | 2b05749d75f0864130027a3df79fc1aa35c691e8 | |
| parent | 9238cad67969e7001e296eaedcdffc63fc38ab30 (diff) | |
scsi: ufs: exynos: Allow max frequencies up to 267Mhz
Platforms such as Tensor gs101 the pclk frequency is 267Mhz. Increase
PCLK_AVAIL_MAX so we don't fail the frequency check.
Signed-off-by: Peter Griffin <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Krzysztof Kozlowski <[email protected]>
Tested-by: Will McVicker <[email protected]>
Signed-off-by: Martin K. Petersen <[email protected]>
| -rw-r--r-- | drivers/ufs/host/ufs-exynos.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h index acf07cc54684..7acc13914100 100644 --- a/drivers/ufs/host/ufs-exynos.h +++ b/drivers/ufs/host/ufs-exynos.h @@ -116,7 +116,7 @@ struct exynos_ufs; #define PA_HIBERN8TIME_VAL 0x20 #define PCLK_AVAIL_MIN 70000000 -#define PCLK_AVAIL_MAX 167000000 +#define PCLK_AVAIL_MAX 267000000 struct exynos_ufs_uic_attr { /* TX Attributes */ |