diff options
| author | Akash Goel <[email protected]> | 2014-03-24 23:00:07 +0530 |
|---|---|---|
| committer | Daniel Vetter <[email protected]> | 2014-06-05 08:52:32 +0200 |
| commit | c98f50628722e2e287656bc7e7492e3d3a0726b8 (patch) | |
| tree | 33b44b8f23e23cb8360a2c5a58f9f3a6c9ceeaaa | |
| parent | 2ab8b458c6a1c784a1edc4308d920f97c0e2a2b8 (diff) | |
drm/i915/vlv: Modifying WA 'WaDisableL3Bank2xClockGate for vlv
For disabling L3 clock gating we need to set bit 25 of MMIO
register 940c. Earlier this was being done by just writing 1
into bit 25 and resetting all other bits.
This patch modifies the routine to read-modify-write of the
register, so that the values of other bits are not destroyed.
v2: Modifying the comments and the patch commit message (Chris)
Signed-off-by: Akash Goel <[email protected]>
Signed-off-by: Sourab Gupta <[email protected]>
Reviewed-by: Damien Lespiau <[email protected]>
[danvet: Apply checkpatch fixup.]
Signed-off-by: Daniel Vetter <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index b86b58c44228..7a4798f52fa1 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5348,8 +5348,11 @@ static void valleyview_init_clock_gating(struct drm_device *dev) I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); - /* WaDisableL3Bank2xClockGate:vlv */ - I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); + /* WaDisableL3Bank2xClockGate:vlv + * Disabling L3 clock gating- MMIO 940c[25] = 1 + * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ + I915_WRITE(GEN7_UCGCTL4, + I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); |