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authorMichael Grzeschik <[email protected]>2023-02-27 16:13:19 +0100
committerVinod Koul <[email protected]>2023-03-31 18:59:16 +0530
commitc8879d3f87ffbaf6954dabec2199905616b0139e (patch)
treeccb6092e07a8da108bf5de7702a42a335183e2c7
parent84a59a314263c21de1b308abda7f7eea92da740d (diff)
phy: stm32-usphyc: add 200 to 300 us delay to fix timeout on some machines
An minimum udelay of 200 us seems to be necessary on some machines. After the setup of the pll, which needs about 100 us to be locked there seem to be additional 100 us to get the phy really functional. Without this delay the usb runs not functional. With this additional short udelay this issue was not reported again. Signed-off-by: Michael Grzeschik <[email protected]> Reviewed-by: Fabrice Gasnier <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
-rw-r--r--drivers/phy/st/phy-stm32-usbphyc.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/phy/st/phy-stm32-usbphyc.c b/drivers/phy/st/phy-stm32-usbphyc.c
index 1add3b75f92f..0a8552628cbd 100644
--- a/drivers/phy/st/phy-stm32-usbphyc.c
+++ b/drivers/phy/st/phy-stm32-usbphyc.c
@@ -317,6 +317,9 @@ static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
stm32_usbphyc_set_bits(pll_reg, PLLEN);
+ /* Wait for maximum lock time */
+ usleep_range(200, 300);
+
return 0;
reg_disable: