diff options
| author | Vladimir Murzin <[email protected]> | 2021-12-01 11:02:58 +0000 |
|---|---|---|
| committer | Marc Zyngier <[email protected]> | 2021-12-02 09:27:06 +0000 |
| commit | c5e0cbe2858d278a27d5b3fe31890aea5be064c4 (patch) | |
| tree | 10771c98bce693f81bef0f234050abfac1e9c6ea | |
| parent | 357a9c4b79f4c8bbceb77c64ea09d8da3a6a870d (diff) | |
irqchip: nvic: Fix offset for Interrupt Priority Offsets
According to ARM(v7M) ARM Interrupt Priority Offsets located at
0xE000E400-0xE000E5EC, while 0xE000E300-0xE000E33C covers read-only
Interrupt Active Bit Registers
Fixes: 292ec080491d ("irqchip: Add support for ARMv7-M NVIC")
Signed-off-by: Vladimir Murzin <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
| -rw-r--r-- | drivers/irqchip/irq-nvic.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/irqchip/irq-nvic.c b/drivers/irqchip/irq-nvic.c index 63bac3f78863..ba4759b3e269 100644 --- a/drivers/irqchip/irq-nvic.c +++ b/drivers/irqchip/irq-nvic.c @@ -26,7 +26,7 @@ #define NVIC_ISER 0x000 #define NVIC_ICER 0x080 -#define NVIC_IPR 0x300 +#define NVIC_IPR 0x400 #define NVIC_MAX_BANKS 16 /* |