diff options
| author | Manivannan Sadhasivam <[email protected]> | 2023-03-14 13:34:36 +0530 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2023-03-15 15:17:21 -0700 |
| commit | c5ccf8d33f11f57ef46d12db1dda4afcc4d5150b (patch) | |
| tree | 66966a645608099f3dc84c5536605f7b7cb51487 | |
| parent | 0fe0955a79b994b8dcabe79f3a7192251fb256ea (diff) | |
arm64: dts: qcom: sm8150: Fix the base addresses of LLCC banks
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.
Reported-by: Parikshit Pareek <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm8150.dtsi | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 55aea7c05ed8..d3e7df92998c 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1794,8 +1794,11 @@ system-cache-controller@9200000 { compatible = "qcom,sm8150-llcc"; - reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, + <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, + <0 0x09600000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; }; |