diff options
| author | Ville Syrjälä <[email protected]> | 2017-08-18 21:37:01 +0300 |
|---|---|---|
| committer | Ville Syrjälä <[email protected]> | 2017-09-15 14:42:55 +0300 |
| commit | c5498089463b94690085158eba7dd29835c8c9b8 (patch) | |
| tree | c2dda55c285bda286d3b94a0266ee480b00dd434 | |
| parent | 3dcf4f207e8e0703cc00d5384e46ed6eb6902613 (diff) | |
drm/i915: Mask everything in ring HWSTAM on gen6+ in ringbuffer mode
The execlist code already masks everything in the ring HWSTAM, but
the ringbuffer code doesn't. Let's go ahead and do that. Pre-gen6
platforms setup HWSTAM during irq setup already since there's just
the one register, and it also contains bits for non-ring interrupts.
Signed-off-by: Ville Syrjälä <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Reviewed-by: Chris Wilson <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 8af8871a8594..22e5ea8516b6 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -428,6 +428,9 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine) mmio = RING_HWS_PGA(engine->mmio_base); } + if (INTEL_GEN(dev_priv) >= 6) + I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff); + I915_WRITE(mmio, engine->status_page.ggtt_offset); POSTING_READ(mmio); |