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authorMario Limonciello <[email protected]>2021-11-04 10:44:50 -0500
committerAlex Deucher <[email protected]>2021-11-05 14:11:43 -0400
commitc451c979eafc3b7ffc1527c724058245ae41b01e (patch)
tree1daad9c8cf5593edfe795aa7b7422679976127d6
parent6ddc0eb7a2e8b731991fe977eb52516fc56ac405 (diff)
drm/amd/pm: Correct DPMS disable IP version check
Previously there was a check based on chip # for chips that aligned to >=CHIP_NAVI10 to have RLC stopped as part of DPMS check. This was because of gfxclk being controlled by RLC in the newer designs. As part of IP version checking though, this got changed to match IP version for SMU. Because Renoir designs also include smu11 that meant that even GFX9 started to stop RLC earlier. Adjust to match GFX IP version instead of SMU IP version to restore the previous behavior. Fixes: a8967967f6a5 ("drm/amdgpu/amdgpu_smu: convert to IP version checking") Signed-off-by: Mario Limonciello <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
-rw-r--r--drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 821ae6e78703..01168b8955bf 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1468,7 +1468,7 @@ static int smu_disable_dpms(struct smu_context *smu)
dev_err(adev->dev, "Failed to disable smu features.\n");
}
- if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0) &&
+ if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0) &&
adev->gfx.rlc.funcs->stop)
adev->gfx.rlc.funcs->stop(adev);