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authorMark Brown <[email protected]>2020-06-22 15:58:32 +0100
committerMark Brown <[email protected]>2020-06-22 15:58:32 +0100
commitc314360cea42e9481d9f68a73a3a776eba31ba4b (patch)
tree2bd3ff996c675e90059c843e130bfdbc0cdd03ee
parent0d574c6b59c6ac0ae5b581a2ffb813d446a50a3d (diff)
parent59ab0fa0c8078f46e747f03191830385f111b35b (diff)
Merge series "Some small spi geni cleanups" from Stephen Boyd <[email protected]>:
To follow onto Doug's latest spi geni series[1] this simplifies and reduces the code a little more. [1] https://lore.kernel.org/r/[email protected] Stephen Boyd (2): spi: spi-geni-qcom: Simplify setup_fifo_xfer() spi: spi-geni-qcom: Don't set {tx,rx}_rem_bytes unnecessarily drivers/spi/spi-geni-qcom.c | 55 +++++++++++++++++-------------------- 1 file changed, 25 insertions(+), 30 deletions(-) base-commit: 7ba9bdcb91f694b0eaf486a825afd9c2d99532b7 -- Sent by a computer, using git, on the internet
-rw-r--r--drivers/spi/spi-geni-qcom.c42
1 files changed, 21 insertions, 21 deletions
diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
index d8f03ffb8594..5b1dca1fff79 100644
--- a/drivers/spi/spi-geni-qcom.c
+++ b/drivers/spi/spi-geni-qcom.c
@@ -122,7 +122,6 @@ static void handle_fifo_timeout(struct spi_master *spi,
reinit_completion(&mas->cancel_done);
writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
mas->cur_xfer = NULL;
- mas->tx_rem_bytes = mas->rx_rem_bytes = 0;
geni_se_cancel_m_cmd(se);
spin_unlock_irq(&mas->lock);
@@ -513,29 +512,30 @@ static irqreturn_t geni_spi_isr(int irq, void *data)
if (mas->cur_xfer) {
spi_finalize_current_transfer(spi);
mas->cur_xfer = NULL;
+ /*
+ * If this happens, then a CMD_DONE came before all the
+ * Tx buffer bytes were sent out. This is unusual, log
+ * this condition and disable the WM interrupt to
+ * prevent the system from stalling due an interrupt
+ * storm.
+ *
+ * If this happens when all Rx bytes haven't been
+ * received, log the condition. The only known time
+ * this can happen is if bits_per_word != 8 and some
+ * registers that expect xfer lengths in num spi_words
+ * weren't written correctly.
+ */
+ if (mas->tx_rem_bytes) {
+ writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
+ dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n",
+ mas->tx_rem_bytes, mas->cur_bits_per_word);
+ }
+ if (mas->rx_rem_bytes)
+ dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n",
+ mas->rx_rem_bytes, mas->cur_bits_per_word);
} else {
complete(&mas->cs_done);
}
-
- /*
- * If this happens, then a CMD_DONE came before all the Tx
- * buffer bytes were sent out. This is unusual, log this
- * condition and disable the WM interrupt to prevent the
- * system from stalling due an interrupt storm.
- * If this happens when all Rx bytes haven't been received, log
- * the condition.
- * The only known time this can happen is if bits_per_word != 8
- * and some registers that expect xfer lengths in num spi_words
- * weren't written correctly.
- */
- if (mas->tx_rem_bytes) {
- writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
- dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n",
- mas->tx_rem_bytes, mas->cur_bits_per_word);
- }
- if (mas->rx_rem_bytes)
- dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n",
- mas->rx_rem_bytes, mas->cur_bits_per_word);
}
if (m_irq & M_CMD_CANCEL_EN)