diff options
| author | Potin Lai <[email protected]> | 2022-12-26 13:45:35 +0800 |
|---|---|---|
| committer | Joel Stanley <[email protected]> | 2023-01-23 14:16:49 +1030 |
| commit | c021d9fe410adadf35a835098073e4528f2db728 (patch) | |
| tree | 88ddbe0601ac612c8084018704ed61e5d6320531 | |
| parent | 107fb95f7ba14f38003218c7e340d8431c2e1d50 (diff) | |
ARM: dts: aspeed: bletchley: Enable wdtrst1
Enable WDTRST1 external signal to send a reset pulse to peripherals while
BMC reset.
Signed-off-by: Potin Lai <[email protected]>
Reviewed-by: Patrick Williams <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Joel Stanley <[email protected]>
| -rw-r--r-- | arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts index 791f83aaac50..e899de681f47 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts @@ -1064,3 +1064,14 @@ bias-disable; }; }; + +&wdt1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; + aspeed,reset-type = "soc"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + aspeed,ext-pulse-duration = <256>; +}; |