diff options
| author | Fabio Estevam <[email protected]> | 2017-08-27 21:25:57 -0300 |
|---|---|---|
| committer | Bjorn Helgaas <[email protected]> | 2017-08-29 13:18:06 -0500 |
| commit | bf2b3312edf182518577d1a28636bd4e9ae00858 (patch) | |
| tree | bac13c9cf9f016b450b6d9390838395e3c5424f9 | |
| parent | 62f9ee98e14521166954e1e0d9fc1ee4ff2a5615 (diff) | |
PCI: rockchip: Use gpiod_set_value_cansleep() to allow reset via expanders
The reset GPIO can be connected to a I2C or SPI IO expander, which may
sleep, so it is safer to use the gpiod_set_value_cansleep() variant
instead.
Signed-off-by: Fabio Estevam <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Shawn Lin <[email protected]>
| -rw-r--r-- | drivers/pci/host/pcie-rockchip.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c index 9ed784360d31..c10b8987d7b3 100644 --- a/drivers/pci/host/pcie-rockchip.c +++ b/drivers/pci/host/pcie-rockchip.c @@ -543,7 +543,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) int err, i; u32 status; - gpiod_set_value(rockchip->ep_gpio, 0); + gpiod_set_value_cansleep(rockchip->ep_gpio, 0); err = reset_control_assert(rockchip->aclk_rst); if (err) { @@ -688,7 +688,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE, PCIE_CLIENT_CONFIG); - gpiod_set_value(rockchip->ep_gpio, 1); + gpiod_set_value_cansleep(rockchip->ep_gpio, 1); /* 500ms timeout value should be enough for Gen1/2 training */ err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1, |