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authorRicardo Neri <[email protected]>2024-06-14 14:16:06 -0700
committerRafael J. Wysocki <[email protected]>2024-06-21 14:52:12 +0200
commitbe6bfb29c55e48567983e24aba7b6bf9a66a45ab (patch)
tree33b72ea937b21f239776f4f2552da5c8dd69e6b4
parent6ae0092ca7adfce79336c6525cb0da561ecd4f04 (diff)
thermal: intel: intel_tcc_cooling: Use a model-specific bitmask for TCC offset
The TCC offset field in the register MSR_TEMPERATURE_TARGET is not architectural. The TCC library provides a model-specific bitmask. Use it to determine the maximum TCC offset. Suggested-by: Zhang Rui <[email protected]> Reviewed-by: Zhang Rui <[email protected]> Signed-off-by: Ricardo Neri <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Rafael J. Wysocki <[email protected]>
-rw-r--r--drivers/thermal/intel/intel_tcc_cooling.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/thermal/intel/intel_tcc_cooling.c b/drivers/thermal/intel/intel_tcc_cooling.c
index 63696e7d7b3c..17110ffa80bb 100644
--- a/drivers/thermal/intel/intel_tcc_cooling.c
+++ b/drivers/thermal/intel/intel_tcc_cooling.c
@@ -20,7 +20,7 @@ static struct thermal_cooling_device *tcc_cdev;
static int tcc_get_max_state(struct thermal_cooling_device *cdev, unsigned long
*state)
{
- *state = 0x3f;
+ *state = intel_tcc_get_offset_mask();
return 0;
}