diff options
author | Cristian Ciocaltea <[email protected]> | 2023-05-04 23:06:48 +0300 |
---|---|---|
committer | Heiko Stuebner <[email protected]> | 2023-05-13 18:40:37 +0200 |
commit | bcac467b7ca045224bd0f35e245b8edfcb1c452e (patch) | |
tree | 1ac26ec7b4e7dcf6912d448505dd5402eeecf4dd | |
parent | d211665c5a833873ee37e501af58adbf028e6b5f (diff) |
arm64: dts: rockchip: Add rk3588 OTP node
Add DT node for Rockchip RK3588/RK3588S OTP memory.
Co-developed-by: Finley Xiao <[email protected]>
Signed-off-by: Finley Xiao <[email protected]>
Signed-off-by: Cristian Ciocaltea <[email protected]>
Tested-by: Vincent Legoll <[email protected]>
[moved cpu-version subnode down, to be sorted by address]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
-rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 944fbe0e8bdb..afcd4e806cf7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -1839,6 +1839,60 @@ status = "disabled"; }; + otp: efuse@fecc0000 { + compatible = "rockchip,rk3588-otp"; + reg = <0x0 0xfecc0000 0x0 0x400>; + clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, + <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; + clock-names = "otp", "apb_pclk", "phy", "arb"; + resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, + <&cru SRST_OTPC_ARB>; + reset-names = "otp", "apb", "arb"; + #address-cells = <1>; + #size-cells = <1>; + + cpu_code: cpu-code@2 { + reg = <0x02 0x2>; + }; + + otp_id: id@7 { + reg = <0x07 0x10>; + }; + + cpub0_leakage: cpu-leakage@17 { + reg = <0x17 0x1>; + }; + + cpub1_leakage: cpu-leakage@18 { + reg = <0x18 0x1>; + }; + + cpul_leakage: cpu-leakage@19 { + reg = <0x19 0x1>; + }; + + log_leakage: log-leakage@1a { + reg = <0x1a 0x1>; + }; + + gpu_leakage: gpu-leakage@1b { + reg = <0x1b 0x1>; + }; + + otp_cpu_version: cpu-version@1c { + reg = <0x1c 0x1>; + bits = <3 3>; + }; + + npu_leakage: npu-leakage@28 { + reg = <0x28 0x1>; + }; + + codec_leakage: codec-leakage@29 { + reg = <0x29 0x1>; + }; + }; + dmac2: dma-controller@fed10000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xfed10000 0x0 0x4000>; |