diff options
| author | Pierre-Louis Bossart <[email protected]> | 2022-08-23 13:38:45 +0800 |
|---|---|---|
| committer | Vinod Koul <[email protected]> | 2022-09-01 14:29:15 +0530 |
| commit | bc7b9595392407549158651bc760c9bda2ab8b5d (patch) | |
| tree | a47501949552f79b9d4d948f070133475398eb15 | |
| parent | 3ea29d33651db069080d1e3b12aea5ef36d766d1 (diff) | |
soundwire: intel: cleanup AC Timing Control
Regroup offset and bitfield definitions
Signed-off-by: Pierre-Louis Bossart <[email protected]>
Reviewed-by: Rander Wang <[email protected]>
Signed-off-by: Bard Liao <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
| -rw-r--r-- | include/linux/soundwire/sdw_intel.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/include/linux/soundwire/sdw_intel.h b/include/linux/soundwire/sdw_intel.h index a2e1927ac8ac..3a56fd5a6331 100644 --- a/include/linux/soundwire/sdw_intel.h +++ b/include/linux/soundwire/sdw_intel.h @@ -76,11 +76,12 @@ #define SDW_SHIM_IOCTL_CIBD BIT(8) #define SDW_SHIM_IOCTL_DIBD BIT(9) -#define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x)) - #define SDW_SHIM_WAKEEN 0x190 #define SDW_SHIM_WAKESTS 0x192 +/* AC Timing control */ +#define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x)) + #define SDW_SHIM_CTMCTL_DACTQE BIT(0) #define SDW_SHIM_CTMCTL_DODS BIT(1) #define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3) |