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authorJack Xiao <[email protected]>2019-05-06 18:55:23 +0800
committerAlex Deucher <[email protected]>2019-06-21 18:59:29 -0500
commitbbd7a6535002289d3ddaf30b8377b492983712df (patch)
treedba9f6927e3a3d97d1f8fe17ba613d1b51bd108a
parent2c195b6cac59e2d60b75ac20379a7a48f5185c2c (diff)
drm/amdgpu/gfx10: require to pin/unpin CSIB BO when suspend/resume
CSIB BO is required to be pinned down to guarantee bo is always valid when resume, and to be unpinned it so that its content can be saved during suspend. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c38
1 files changed, 38 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index b7b761f7e34e..1e67bf1f585d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -813,6 +813,39 @@ static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
return 0;
}
+static int gfx_v10_0_csb_vram_pin(struct amdgpu_device *adev)
+{
+ int r;
+
+ r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
+ if (unlikely(r != 0))
+ return r;
+
+ r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
+ AMDGPU_GEM_DOMAIN_VRAM);
+ if (!r)
+ adev->gfx.rlc.clear_state_gpu_addr =
+ amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
+
+ amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+
+ return r;
+}
+
+static void gfx_v10_0_csb_vram_unpin(struct amdgpu_device *adev)
+{
+ int r;
+
+ if (!adev->gfx.rlc.clear_state_obj)
+ return;
+
+ r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
+ if (likely(r == 0)) {
+ amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
+ amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+ }
+}
+
static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
{
amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
@@ -3494,6 +3527,10 @@ static int gfx_v10_0_hw_init(void *handle)
int r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ r = gfx_v10_0_csb_vram_pin(adev);
+ if (r)
+ return r;
+
if (!amdgpu_emu_mode)
gfx_v10_0_init_golden_registers(adev);
@@ -3581,6 +3618,7 @@ static int gfx_v10_0_hw_fini(void *handle)
}
gfx_v10_0_cp_enable(adev, false);
gfx_v10_0_enable_gui_idle_interrupt(adev, false);
+ gfx_v10_0_csb_vram_unpin(adev);
return 0;
}