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authorAhmad Fatoum <[email protected]>2020-08-28 15:00:02 +0200
committerAlexandre Torgue <[email protected]>2020-09-23 18:37:02 +0200
commitbae2b7f6774b2db44f9001bee7465d4dadd1ede8 (patch)
treebf6c475fd420b35fe5e87e76b1a4dc7f011c90af
parent57592d2a98dbc3bde3ddc062e91a8486bdcb211e (diff)
ARM: dts: stm32: lxa-mc1: enable DDR50 mode on eMMC
The "eMMC high-speed DDR mode (3.3V I/O)" at 50MHz is supported on the eMMC-interface of the lxa-mc1. Set it in the device tree to benefit from the speed improvement. Signed-off-by: Ahmad Fatoum <[email protected]> Signed-off-by: Holger Assmann <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
-rw-r--r--arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts
index b85025d00943..1e5333fd437f 100644
--- a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts
@@ -212,6 +212,7 @@
pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_b>;
pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_b>;
bus-width = <8>;
+ mmc-ddr-3_3v;
no-1-8-v;
no-sd;
no-sdio;