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authorRoger Quadros <[email protected]>2020-09-30 15:20:27 +0300
committerNishanth Menon <[email protected]>2020-09-30 07:34:02 -0500
commitba90e0c92666979298a2c42ca396ac56d00cf33e (patch)
treeea0316337cf65cc00cdcc0223dff2a53eacbe371
parentffb0024ecd3d3e20b8eb1d0d54ceeb7f43453118 (diff)
dt-bindings: ti-serdes-mux: Add defines for J7200 SoC
There are 4 lanes in each J7200 SERDES. Each SERDES lane mux can select upto 4 different IPs. Define all the possible functions. Signed-off-by: Roger Quadros <[email protected]> Signed-off-by: Nishanth Menon <[email protected]> Reviewed-by: Vignesh Raghavendra <[email protected]> Acked-by: Rob Herring <[email protected]> Acked-by: Peter Rosin <[email protected]> Cc: Peter Rosin <[email protected]> Link: https://lore.kernel.org/r/[email protected]
-rw-r--r--include/dt-bindings/mux/ti-serdes.h22
1 files changed, 22 insertions, 0 deletions
diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h
index 146d0685a925..9047ec6bd3cf 100644
--- a/include/dt-bindings/mux/ti-serdes.h
+++ b/include/dt-bindings/mux/ti-serdes.h
@@ -68,4 +68,26 @@
#define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2
#define J721E_SERDES4_LANE3_IP4_UNUSED 0x3
+/* J7200 */
+
+#define J7200_SERDES0_LANE0_QSGMII_LANE3 0x0
+#define J7200_SERDES0_LANE0_PCIE1_LANE0 0x1
+#define J7200_SERDES0_LANE0_IP3_UNUSED 0x2
+#define J7200_SERDES0_LANE0_IP4_UNUSED 0x3
+
+#define J7200_SERDES0_LANE1_QSGMII_LANE4 0x0
+#define J7200_SERDES0_LANE1_PCIE1_LANE1 0x1
+#define J7200_SERDES0_LANE1_IP3_UNUSED 0x2
+#define J7200_SERDES0_LANE1_IP4_UNUSED 0x3
+
+#define J7200_SERDES0_LANE2_QSGMII_LANE1 0x0
+#define J7200_SERDES0_LANE2_PCIE1_LANE2 0x1
+#define J7200_SERDES0_LANE2_IP3_UNUSED 0x2
+#define J7200_SERDES0_LANE2_IP4_UNUSED 0x3
+
+#define J7200_SERDES0_LANE3_QSGMII_LANE2 0x0
+#define J7200_SERDES0_LANE3_PCIE1_LANE3 0x1
+#define J7200_SERDES0_LANE3_USB 0x2
+#define J7200_SERDES0_LANE3_IP4_UNUSED 0x3
+
#endif /* _DT_BINDINGS_MUX_TI_SERDES */