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authorAnshuman Khandual <[email protected]>2023-06-14 12:29:40 +0530
committerCatalin Marinas <[email protected]>2023-06-14 14:37:33 +0100
commitb7c3a6eb4d2b6abf9aa2b08d70e5fc9008797a86 (patch)
tree853343e225fe326c2f148e923383cd417bc8535c
parent7bb948826610f05b42567ce89156d6513d53d988 (diff)
arm64/sysreg: Rename TRBMAR_EL1 fields per auto-gen tools format
This renames TRBMAR_EL1 register fields per auto-gen tools format without causing any functional change in the TRBE driver. Cc: Will Deacon <[email protected]> Cc: Marc Zyngier <[email protected]> Cc: Mark Brown <[email protected]> Cc: Rob Herring <[email protected]> Cc: Suzuki K Poulose <[email protected]> Cc: James Morse <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Signed-off-by: Anshuman Khandual <[email protected]> Reviewed-by: Suzuki K Poulose <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Catalin Marinas <[email protected]>
-rw-r--r--arch/arm64/include/asm/sysreg.h10
1 files changed, 4 insertions, 6 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 1df57d672a65..ef8c9d81b6ad 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -263,12 +263,10 @@
#define TRBSR_EL1_BSC_SHIFT 0
#define TRBSR_EL1_FSC_MASK GENMASK(5, 0)
#define TRBSR_EL1_FSC_SHIFT 0
-#define TRBMAR_SHARE_MASK GENMASK(1, 0)
-#define TRBMAR_SHARE_SHIFT 8
-#define TRBMAR_OUTER_MASK GENMASK(3, 0)
-#define TRBMAR_OUTER_SHIFT 4
-#define TRBMAR_INNER_MASK GENMASK(3, 0)
-#define TRBMAR_INNER_SHIFT 0
+#define TRBMAR_EL1_SH_MASK GENMASK(9, 8)
+#define TRBMAR_EL1_SH_SHIFT 8
+#define TRBMAR_EL1_Attr_MASK GENMASK(7, 0)
+#define TRBMAR_EL1_Attr_SHIFT 0
#define TRBTRG_TRG_MASK GENMASK(31, 0)
#define TRBTRG_TRG_SHIFT 0
#define TRBIDR_FLAG BIT(5)