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authorZhifeng Tang <[email protected]>2023-08-24 17:26:24 +0800
committerStephen Boyd <[email protected]>2023-09-11 13:50:49 -0700
commitb7b20cfe6f849c2682c5f7d3f50ede6321a5d04c (patch)
tree849c1e16631688614b7c1bef7c0fc0940de2a5fa
parenteec11486d191c6247e6ffdc898bc31da3cfadcce (diff)
clk: sprd: Fix thm_parents incorrect configuration
The thm*_clk have two clock sources 32k and 250k,excluding 32m. Fixes: af3bd36573e3 ("clk: sprd: Add clocks support for UMS512") Signed-off-by: Zhifeng Tang <[email protected]> Acked-by: Chunyan Zhang <[email protected]> Reviewed-by: Baolin Wang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
-rw-r--r--drivers/clk/sprd/ums512-clk.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/sprd/ums512-clk.c b/drivers/clk/sprd/ums512-clk.c
index 8f4441dd572b..9384ecc6c741 100644
--- a/drivers/clk/sprd/ums512-clk.c
+++ b/drivers/clk/sprd/ums512-clk.c
@@ -800,7 +800,7 @@ static SPRD_MUX_CLK_DATA(uart1_clk, "uart1-clk", uart_parents,
0x250, 0, 3, UMS512_MUX_FLAG);
static const struct clk_parent_data thm_parents[] = {
- { .fw_name = "ext-32m" },
+ { .fw_name = "ext-32k" },
{ .hw = &clk_250k.hw },
};
static SPRD_MUX_CLK_DATA(thm0_clk, "thm0-clk", thm_parents,