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authorJoey Gouly <[email protected]>2024-08-22 16:10:56 +0100
committerWill Deacon <[email protected]>2024-09-04 12:52:40 +0100
commitb66db4f3ccde2fe960ff2d7bb64fe8933e2db7b3 (patch)
tree54ef013201c1ed0f8ceb101edf4edaf7e5c5c8fb
parentfacaa1373c9aabf8e34109a9cb205ad0f3a8584e (diff)
arm64: add POIndex defines
The 3-bit POIndex is stored in the PTE at bits 60..62. Signed-off-by: Joey Gouly <[email protected]> Cc: Catalin Marinas <[email protected]> Cc: Will Deacon <[email protected]> Acked-by: Catalin Marinas <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Will Deacon <[email protected]>
-rw-r--r--arch/arm64/include/asm/pgtable-hwdef.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
index 1f60aa1bc750..3f0c3f5c5cef 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -200,6 +200,16 @@
#define PTE_PI_IDX_3 54 /* UXN */
/*
+ * POIndex[2:0] encoding (Permission Overlay Extension)
+ */
+#define PTE_PO_IDX_0 (_AT(pteval_t, 1) << 60)
+#define PTE_PO_IDX_1 (_AT(pteval_t, 1) << 61)
+#define PTE_PO_IDX_2 (_AT(pteval_t, 1) << 62)
+
+#define PTE_PO_IDX_MASK GENMASK_ULL(62, 60)
+
+
+/*
* Memory Attribute override for Stage-2 (MemAttr[3:0])
*/
#define PTE_S2_MEMATTR(t) (_AT(pteval_t, (t)) << 2)