diff options
| author | Robert Marko <[email protected]> | 2023-01-13 17:44:44 +0100 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2023-01-18 21:15:06 -0600 |
| commit | b60590314828e3da670bed94129f4ebc02b87548 (patch) | |
| tree | 6c6e5edaaaf05cfed2e62d3e263fb970931fb228 | |
| parent | 2055cb7dccea16bafa3adf9c5e3216949512c34a (diff) | |
arm64: dts: qcom: ipq8074: set Gen2 PCIe pcie max-link-speed
Add the generic 'max-link-speed' property to describe the Gen2 PCIe link
generation limit.
This allows the generic DWC code to configure the link speed correctly.
Signed-off-by: Robert Marko <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
| -rw-r--r-- | arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index bb9768b9becc..96533bc54ac6 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -766,6 +766,7 @@ linux,pci-domain = <1>; bus-range = <0x00 0xff>; num-lanes = <1>; + max-link-speed = <2>; #address-cells = <3>; #size-cells = <2>; |