diff options
| author | Dan Carpenter <[email protected]> | 2024-01-26 11:40:37 +0300 |
|---|---|---|
| committer | Bjorn Helgaas <[email protected]> | 2024-02-07 13:09:02 -0600 |
| commit | b5d1b4b46f856da1473c7ba9a5cdfcb55c9b2478 (patch) | |
| tree | dbcb27cef1bd09a3347fb71e9d0743457c5d4857 | |
| parent | 6613476e225e090cc9aad49be7fa504e290dd33d (diff) | |
PCI: dwc: Fix a 64bit bug in dw_pcie_ep_raise_msix_irq()
The "msg_addr" variable is u64. However, the "aligned_offset" is an
unsigned int. This means that when the code does:
msg_addr &= ~aligned_offset;
it will unintentionally zero out the high 32 bits. Use ALIGN_DOWN() to do
the alignment instead.
Fixes: 2217fffcd63f ("PCI: dwc: endpoint: Fix dw_pcie_ep_raise_msix_irq() alignment support")
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Dan Carpenter <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Niklas Cassel <[email protected]>
Reviewed-by: Ilpo Järvinen <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Cc: <[email protected]>
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-designware-ep.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 5befed2dc02b..d6b66597101e 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -6,6 +6,7 @@ * Author: Kishon Vijay Abraham I <[email protected]> */ +#include <linux/align.h> #include <linux/bitfield.h> #include <linux/of.h> #include <linux/platform_device.h> @@ -551,7 +552,7 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, } aligned_offset = msg_addr & (epc->mem->window.page_size - 1); - msg_addr &= ~aligned_offset; + msg_addr = ALIGN_DOWN(msg_addr, epc->mem->window.page_size); ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr, epc->mem->window.page_size); if (ret) |