diff options
| author | Konrad Dybcio <[email protected]> | 2023-03-31 03:14:52 +0200 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2023-04-07 16:33:26 -0700 |
| commit | b53ae6b63181f4575fc62cd0efb341c8151b0a74 (patch) | |
| tree | 22ef34701e7113ec56766ed15a444a1f2af8dfb1 | |
| parent | 1642ab96efa427f88e8a54c11b01b1b333ce58bd (diff) | |
arm64: dts: qcom: sm8150: Add GPU speedbin support
SM8150 has (at least) two GPU speed bins. With the support added on the
driver side, wire up bin detection in the DTS to restrict lower-quality
SKUs from running at frequencies they were not validated at.
Tested-by: Marijn Suijten <[email protected]> # On Sony Xperia 5 (speed bin 0x3)
Reviewed-by: Marijn Suijten <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Konrad Dybcio <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm8150.dtsi | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 39e43a46bb30..2273fa571988 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -950,6 +950,17 @@ status = "disabled"; }; + qfprom: efuse@784000 { + compatible = "qcom,sm8150-qfprom", "qcom,qfprom"; + reg = <0 0x00784000 0 0x8ff>; + #address-cells = <1>; + #size-cells = <1>; + + gpu_speed_bin: gpu_speed_bin@133 { + reg = <0x133 0x1>; + bits = <5 3>; + }; + }; qupv3_id_0: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; @@ -2165,44 +2176,52 @@ qcom,gmu = <&gmu>; + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + status = "disabled"; zap-shader { memory-region = <&gpu_mem>; }; - /* note: downstream checks gpu binning for 675 Mhz */ gpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-675000000 { opp-hz = /bits/ 64 <675000000>; opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + opp-supported-hw = <0x2>; }; opp-585000000 { opp-hz = /bits/ 64 <585000000>; opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + opp-supported-hw = <0x3>; }; opp-499200000 { opp-hz = /bits/ 64 <499200000>; opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; + opp-supported-hw = <0x3>; }; opp-427000000 { opp-hz = /bits/ 64 <427000000>; opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + opp-supported-hw = <0x3>; }; opp-345000000 { opp-hz = /bits/ 64 <345000000>; opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + opp-supported-hw = <0x3>; }; opp-257000000 { opp-hz = /bits/ 64 <257000000>; opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + opp-supported-hw = <0x3>; }; }; }; |