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authorPeter Zijlstra <[email protected]>2016-05-30 14:32:04 +0200
committerIngo Molnar <[email protected]>2016-06-14 11:55:15 +0200
commitb464d1270a8016edcf1fd20d77cefdecf9b0b73e (patch)
tree2648743895f108c3e2aa9157313c8449404b5883
parent7cb45c0fe9858f92cc264f6bf9d2f6a0e7d3b249 (diff)
locking/barriers, tile: Provide TILE specific smp_acquire__after_ctrl_dep()
Since TILE doesn't do read speculation, its control dependencies also guarantee LOAD->LOAD order and we don't need the additional RMB otherwise required to provide ACQUIRE semantics. Signed-off-by: Peter Zijlstra (Intel) <[email protected]> Acked-by: Chris Metcalf <[email protected]> Cc: Andrew Morton <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Paul E. McKenney <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: [email protected] Signed-off-by: Ingo Molnar <[email protected]>
-rw-r--r--arch/tile/include/asm/barrier.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/tile/include/asm/barrier.h b/arch/tile/include/asm/barrier.h
index d55222806c2f..4c419ab95ab7 100644
--- a/arch/tile/include/asm/barrier.h
+++ b/arch/tile/include/asm/barrier.h
@@ -87,6 +87,13 @@ mb_incoherent(void)
#define __smp_mb__after_atomic() __smp_mb()
#endif
+/*
+ * The TILE architecture does not do speculative reads; this ensures
+ * that a control dependency also orders against loads and already provides
+ * a LOAD->{LOAD,STORE} order and can forgo the additional RMB.
+ */
+#define smp_acquire__after_ctrl_dep() barrier()
+
#include <asm-generic/barrier.h>
#endif /* !__ASSEMBLY__ */