diff options
| author | Gaku Inami <[email protected]> | 2018-11-08 16:24:54 +0900 |
|---|---|---|
| committer | Simon Horman <[email protected]> | 2018-11-15 06:27:03 -0800 |
| commit | b380ae0db6039131fd0ad985b760c5b3f5096dfc (patch) | |
| tree | f72da46aacf80d46b41667b5319215a85a630948 | |
| parent | 8ebb50389eed04b989a0d5532f9208c338bf66b8 (diff) | |
arm64: dts: renesas: Add CPU topology on R-Car Gen3 SoCs
This patch adds the "cpu-map" into r8a7795/r8a7796 composed of
multi-cluster. This definition is used to parse the cpu topology.
Signed-off-by: Gaku Inami <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a7795.dtsi | 32 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a7796.dtsi | 26 |
2 files changed, 58 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 660fd54d384b..408ff4e8170a 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -116,6 +116,38 @@ #address-cells = <1>; #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&a57_0>; + }; + core1 { + cpu = <&a57_1>; + }; + core2 { + cpu = <&a57_2>; + }; + core3 { + cpu = <&a57_3>; + }; + }; + + cluster1 { + core0 { + cpu = <&a53_0>; + }; + core1 { + cpu = <&a53_1>; + }; + core2 { + cpu = <&a53_2>; + }; + core3 { + cpu = <&a53_3>; + }; + }; + }; + a57_0: cpu@0 { compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x0>; diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 3baee26ae372..b12bf73bb03b 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -127,6 +127,32 @@ #address-cells = <1>; #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&a57_0>; + }; + core1 { + cpu = <&a57_1>; + }; + }; + + cluster1 { + core0 { + cpu = <&a53_0>; + }; + core1 { + cpu = <&a53_1>; + }; + core2 { + cpu = <&a53_2>; + }; + core3 { + cpu = <&a53_3>; + }; + }; + }; + a57_0: cpu@0 { compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x0>; |