diff options
| author | Joel Stanley <[email protected]> | 2020-07-24 12:00:35 +0930 |
|---|---|---|
| committer | Joel Stanley <[email protected]> | 2020-07-24 14:49:03 +0930 |
| commit | b23b2b842002424147b820f22d52a8306bd7b2ac (patch) | |
| tree | ae76631e271c90df76d603ca4611a337efaf2c4e | |
| parent | 0ce0581e6d32040696effd1b2298618c3aa3a595 (diff) | |
ARM: dts: aspeed: rainier: Add CFAM reset GPIO
The GPIO on Q0 is used for resetting the CFAM of the processor that the
ASPEED master is connected to.
The signal is wired as active high on the first pass systems.
Reviewed-by: Andrew Jeffery <[email protected]>
Signed-off-by: Joel Stanley <[email protected]>
| -rw-r--r-- | arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index ac7cc96a15d3..e91f3bc7a0c2 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -125,6 +125,12 @@ #address-cells = <2>; #size-cells = <0>; + /* + * CFAM Reset is supposed to be active low but pass1 hardware is wired + * active high. + */ + cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>; + cfam@0,0 { reg = <0 0>; #address-cells = <1>; |