diff options
| author | Sibi Sankar <[email protected]> | 2020-02-27 16:26:31 +0530 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2020-03-05 21:47:05 -0800 |
| commit | b21bb61d243a12d993a498947e8fbd9045f44182 (patch) | |
| tree | 59f25c93afafd333bbc6a8cc214c4e9b4dd081fe | |
| parent | 74f26599809c870c2d744332591e7622b104de26 (diff) | |
arm64: dts: qcom: sc7180: Add OSM L3 interconnect provider
Add Operation State Manager (OSM) L3 interconnect provider on SC7180 SoCs.
Acked-by: Georgi Djakov <[email protected]>
Reviewed-by: Evan Green <[email protected]>
Signed-off-by: Sibi Sankar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sc7180.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 959221365266..c51fda655195 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1988,6 +1988,16 @@ }; }; + osm_l3: interconnect@18321000 { + compatible = "qcom,sc7180-osm-l3"; + reg = <0 0x18321000 0 0x1400>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@18323000 { compatible = "qcom,cpufreq-hw"; reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; |