diff options
| author | Clinton A Taylor <[email protected]> | 2020-10-21 01:20:30 -0700 |
|---|---|---|
| committer | Lucas De Marchi <[email protected]> | 2020-10-23 17:16:06 -0700 |
| commit | b18c1eb975ce181996310a526582a3ddbc6735e9 (patch) | |
| tree | 48c493c1bb59bdb732efded6598d240cbd7be0de | |
| parent | 229f31e2d370d36c2345dadb821c856f61d13197 (diff) | |
drm/i915/dg1: invert HPD pins
HPD pins are inverted for DG1 platform.
Bspec: 49956
Cc: José Roberto de Souza <[email protected]>
Cc: Matt Roper <[email protected]>
Signed-off-by: Clinton A Taylor <[email protected]>
Reviewed-by: Lucas De Marchi <[email protected]>
Signed-off-by: Lucas De Marchi <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
| -rw-r--r-- | drivers/gpu/drm/i915/i915_irq.c | 9 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 4 |
2 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 4ac4139524a3..dc33c96d741d 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3268,6 +3268,15 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv) static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv) { + u32 val; + + val = I915_READ(SOUTH_CHICKEN1); + val |= (INVERT_DDIA_HPD | + INVERT_DDIB_HPD | + INVERT_DDIC_HPD | + INVERT_DDID_HPD); + I915_WRITE(SOUTH_CHICKEN1, val); + icp_hpd_irq_setup(dev_priv, DG1_DDI_HPD_ENABLE_MASK, 0); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5f0136578de0..8b021f77cb1f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8727,6 +8727,10 @@ enum { #define SOUTH_CHICKEN1 _MMIO(0xc2000) #define FDIA_PHASE_SYNC_SHIFT_OVR 19 #define FDIA_PHASE_SYNC_SHIFT_EN 18 +#define INVERT_DDID_HPD (1 << 18) +#define INVERT_DDIC_HPD (1 << 17) +#define INVERT_DDIB_HPD (1 << 16) +#define INVERT_DDIA_HPD (1 << 15) #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) #define FDI_BC_BIFURCATION_SELECT (1 << 12) |