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authorLijo Lazar <[email protected]>2023-11-30 16:35:58 +0530
committerAlex Deucher <[email protected]>2023-12-06 15:22:37 -0500
commitb12fb2953915b092aaef956f6e80783fa70b9f40 (patch)
tree7fbe8307796a27a0ebbf57204b425ea7f6380fa6
parent828afefd4b0636d92386d4b2c1f53fff87505aba (diff)
drm/amdgpu: Avoid querying DRM MGCG status
MP0 v13.0.6 SOCs don't support DRM MGCG. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/soc15.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 9043ebf1e161..15033efec2ba 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1430,7 +1430,8 @@ static void soc15_common_get_clockgating_state(void *handle, u64 *flags)
if (adev->hdp.funcs && adev->hdp.funcs->get_clock_gating_state)
adev->hdp.funcs->get_clock_gating_state(adev, flags);
- if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) {
+ if ((amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) &&
+ (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6))) {
/* AMD_CG_SUPPORT_DRM_MGCG */
data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
if (!(data & 0x01000000))