diff options
| author | Ian Rogers <[email protected]> | 2023-02-22 21:53:04 -0800 |
|---|---|---|
| committer | Arnaldo Carvalho de Melo <[email protected]> | 2023-02-27 18:41:24 -0300 |
| commit | b0365c147f7b2aeb500456601bf6a3e08133b178 (patch) | |
| tree | d75ff8a357232dcf2bad87b1a2c45a2aad3dd487 | |
| parent | aa0964e3ecebe92243bac30f9317117037adecb9 (diff) | |
perf vendor events intel: Update alderlake to v1.19
Update alderlake perf json from v1.18 to v1.19.
Based on:
https://github.com/intel/perfmon/pull/58
perf JSON files created using:
https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py
Signed-off-by: Ian Rogers <[email protected]>
Cc: Alexander Shishkin <[email protected]>
Cc: Edward Baker <[email protected]>
Cc: Ingo Molnar <[email protected]>
Cc: Jiri Olsa <[email protected]>
Cc: Kan Liang <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Namhyung Kim <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Xing Zhengjun <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/alderlake/memory.json | 8 | ||||
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/alderlake/pipeline.json | 10 | ||||
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/mapfile.csv | 2 |
3 files changed, 19 insertions, 1 deletions
diff --git a/tools/perf/pmu-events/arch/x86/alderlake/memory.json b/tools/perf/pmu-events/arch/x86/alderlake/memory.json index 37f3d062a788..55827b276e6e 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/memory.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/memory.json @@ -25,6 +25,14 @@ "Unit": "cpu_atom" }, { + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss.", + "EventCode": "0x05", + "EventName": "LD_HEAD.L1_MISS_AT_RET", + "SampleAfterValue": "1000003", + "UMask": "0x81", + "Unit": "cpu_atom" + }, + { "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.", "EventCode": "0x05", "EventName": "LD_HEAD.OTHER_AT_RET", diff --git a/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json b/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json index 2dba3a115f97..f848530fbf07 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json @@ -362,6 +362,16 @@ "Unit": "cpu_atom" }, { + "BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.INDIRECT", + "PEBS": "1", + "PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.", + "SampleAfterValue": "100003", + "UMask": "0x80", + "Unit": "cpu_core" + }, + { "BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired.", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index 1c6eef118e61..e69b29123327 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -1,5 +1,5 @@ Family-model,Version,Filename,EventType -GenuineIntel-6-(97|9A|B7|BA|BF),v1.18,alderlake,core +GenuineIntel-6-(97|9A|B7|BA|BF),v1.19,alderlake,core GenuineIntel-6-BE,v1.18,alderlaken,core GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core GenuineIntel-6-(3D|47),v26,broadwell,core |