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authorImre Deak <[email protected]>2022-04-21 19:22:21 +0300
committerImre Deak <[email protected]>2022-04-25 14:45:33 +0300
commitaf2cbc6ef967f61711a3c40fca5366ea0bc7fecc (patch)
treeec580bb1f2c4fd1685774038c6efd84c8103ebba
parent1e1d2e185358b9383807ccfc30f51b642ebe3b8a (diff)
drm/i915: Fix SEL_FETCH_PLANE_*(PIPE_B+) register addresses
Fix typo in the _SEL_FETCH_PLANE_BASE_1_B register base address. Fixes: a5523e2ff074a5 ("drm/i915: Add PSR2 selective fetch registers") References: https://gitlab.freedesktop.org/drm/intel/-/issues/5400 Cc: José Roberto de Souza <[email protected]> Cc: <[email protected]> # v5.9+ Signed-off-by: Imre Deak <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index aa0062d07269..c997bd604c49 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5161,7 +5161,7 @@
#define _SEL_FETCH_PLANE_BASE_6_A 0x70940
#define _SEL_FETCH_PLANE_BASE_7_A 0x70960
#define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880
-#define _SEL_FETCH_PLANE_BASE_1_B 0x70990
+#define _SEL_FETCH_PLANE_BASE_1_B 0x71890
#define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \
_SEL_FETCH_PLANE_BASE_1_A, \