diff options
| author | Nishanth Menon <[email protected]> | 2021-01-20 13:51:45 -0600 |
|---|---|---|
| committer | Nishanth Menon <[email protected]> | 2021-01-28 08:51:18 -0600 |
| commit | ae10ce938da59c19f303a91197ea7d664d1bc080 (patch) | |
| tree | a175222ce9c8b210adb24f41c23953dbe6ef759e | |
| parent | 0cf73209ce2c60c5b717a02d9de10a6d524e08a6 (diff) | |
arm64: dts: ti: k3*: Fixup PMU compatibility to be CPU specific
We can use CPU specific pmu configuration to expose the appropriate
CPU specific events rather than just the basic generic pmuv3 perf
events.
Reported-by: Sudeep Holla <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
Tested-by: Suman Anna <[email protected]>
Reviewed-by: Tero Kristo <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-am65.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-j7200.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-j721e.dtsi | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi index d84c0bc05023..a9fc1af03f27 100644 --- a/arch/arm64/boot/dts/ti/k3-am65.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi @@ -56,7 +56,7 @@ }; pmu: pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; /* Recommendation from GIC500 TRM Table A.3 */ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi index 66169bcf7c9a..b7005b803149 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi @@ -114,7 +114,7 @@ }; pmu: pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a72-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index cc483f7344af..f0587fde147e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -115,7 +115,7 @@ }; pmu: pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a72-pmu"; /* Recommendation from GIC500 TRM Table A.3 */ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; }; |