diff options
| author | Walker Chen <[email protected]> | 2023-07-24 14:51:57 +0800 |
|---|---|---|
| committer | Conor Dooley <[email protected]> | 2023-07-26 17:18:03 +0100 |
| commit | ac73c09716c3d0da3f0606e282e99c2a8c0a9afc (patch) | |
| tree | dc412ea44e30c241434885a6cfb7c20ada7672a9 | |
| parent | 74fb20c8f05df7a7ea5c98ca85a713758e0e59f6 (diff) | |
riscv: dts: starfive: jh7110: add dma controller node
Add the dma controller node for the Starfive JH7110 SoC.
Reviewed-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Walker Chen <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index ecd4160b2f54..1a65f6848560 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -843,6 +843,24 @@ status = "disabled"; }; + dma: dma-controller@16050000 { + compatible = "starfive,jh7110-axi-dma"; + reg = <0x0 0x16050000 0x0 0x10000>; + clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>, + <&stgcrg JH7110_STGCLK_DMA1P_AHB>; + clock-names = "core-clk", "cfgr-clk"; + resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>, + <&stgcrg JH7110_STGRST_DMA1P_AHB>; + interrupts = <73>; + #dma-cells = <1>; + dma-channels = <4>; + snps,dma-masters = <1>; + snps,data-width = <3>; + snps,block-size = <65536 65536 65536 65536>; + snps,priority = <0 1 2 3>; + snps,axi-max-burst-len = <16>; + }; + aoncrg: clock-controller@17000000 { compatible = "starfive,jh7110-aoncrg"; reg = <0x0 0x17000000 0x0 0x10000>; |