diff options
| author | Chen-Yu Tsai <[email protected]> | 2020-03-11 01:47:08 +0800 |
|---|---|---|
| committer | Chen-Yu Tsai <[email protected]> | 2020-03-11 22:47:58 +0800 |
| commit | abe076fb0dfd34e4b8b397946d5e1dab2d7fe953 (patch) | |
| tree | a8a8ab84defdfd42556d34871c7a258f859fe16f | |
| parent | fe3a04824f75786e39ed74e82fb6cb2534c95fe4 (diff) | |
ARM: dts: sun8i: r40: Fix register base address for SPI2 and SPI3
When the SPI device nodes were added, SPI2 and SPI3 had incorrect
register base addresses.
Fix the base address for both of them.
Fixes: 554581b79139 ("ARM: dts: sun8i: R40: Add SPI controllers nodes and pinmuxes")
Reported-by: JuanEsf <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Chen-Yu Tsai <[email protected]>
| -rw-r--r-- | arch/arm/boot/dts/sun8i-r40.dtsi | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index bb606eaa8d4c..43c92391bd2b 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -689,10 +689,10 @@ #size-cells = <0>; }; - spi2: spi@1c07000 { + spi2: spi@1c17000 { compatible = "allwinner,sun8i-r40-spi", "allwinner,sun8i-h3-spi"; - reg = <0x01c07000 0x1000>; + reg = <0x01c17000 0x1000>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>; clock-names = "ahb", "mod"; @@ -702,10 +702,10 @@ #size-cells = <0>; }; - spi3: spi@1c0f000 { + spi3: spi@1c1f000 { compatible = "allwinner,sun8i-r40-spi", "allwinner,sun8i-h3-spi"; - reg = <0x01c0f000 0x1000>; + reg = <0x01c1f000 0x1000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>; clock-names = "ahb", "mod"; |