diff options
| author | Icenowy Zheng <uwu@icenowy.me> | 2023-02-02 15:28:14 +0800 |
|---|---|---|
| committer | Daniel Lezcano <daniel.lezcano@linaro.org> | 2023-02-13 13:10:17 +0100 |
| commit | abd873afc889c0b4348ec4b567d83f97df8edaf6 (patch) | |
| tree | 7eab1b5346810d6d7916943649e6a070562f9c56 | |
| parent | 27788e01a6507c882946b9aa87318c3185cd83e6 (diff) | |
dt-bindings: timer: sifive,clint: add comaptibles for T-Head's C9xx
T-Head C906/C910 CLINT is not compliant to SiFive ones (and even not
compliant to the newcoming ACLINT spec) because of lack of mtime
register.
Add a compatible string formatted like the C9xx-specific PLIC
compatible, and do not allow a SiFive one as fallback because they're
not really compliant.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230202072814.319903-1-uwu@icenowy.me
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| -rw-r--r-- | Documentation/devicetree/bindings/timer/sifive,clint.yaml | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index bbad24165837..aada6957216c 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -20,6 +20,10 @@ description: property of "/cpus" DT node. The "timebase-frequency" DT property is described in Documentation/devicetree/bindings/riscv/cpus.yaml + T-Head C906/C910 CPU cores include an implementation of CLINT too, however + their implementation lacks a memory-mapped MTIME register, thus not + compatible with SiFive ones. + properties: compatible: oneOf: @@ -30,6 +34,10 @@ properties: - canaan,k210-clint - const: sifive,clint0 - items: + - enum: + - allwinner,sun20i-d1-clint + - const: thead,c900-clint + - items: - const: sifive,clint0 - const: riscv,clint0 deprecated: true |