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authorMatt Roper <[email protected]>2023-02-23 16:23:00 -0800
committerMatt Roper <[email protected]>2023-02-28 11:58:58 -0800
commitabd74d262b07f33d6c298f1b2fe03cfcdb3c72f7 (patch)
tree360d2cb3394c6169ac58998fb4720b518fb983cd
parentcebc13de7e704b1355bea208a9f9cdb042c74588 (diff)
drm/i915: Stop whitelisting CS_CTX_TIMESTAMP on Xe_HP platforms
Xe_HP architecture already makes the CS_CTX_TIMESTAMP readable by userspace on all engines; there's no longer a need to add it to the software-managed whitelist for the non-RCS engines. Bspec: 45545 Signed-off-by: Matt Roper <[email protected]> Acked-by: Gustavo Sousa <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
-rw-r--r--drivers/gpu/drm/i915/gt/intel_workarounds.c11
1 files changed, 1 insertions, 10 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 5461628d221d..5a1c56c0901e 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2251,17 +2251,10 @@ static void dg1_whitelist_build(struct intel_engine_cs *engine)
RING_FORCE_TO_NONPRIV_ACCESS_RD);
}
-static void xehpsdv_whitelist_build(struct intel_engine_cs *engine)
-{
- allow_read_ctx_timestamp(engine);
-}
-
static void dg2_whitelist_build(struct intel_engine_cs *engine)
{
struct i915_wa_list *w = &engine->whitelist;
- allow_read_ctx_timestamp(engine);
-
switch (engine->class) {
case RENDER_CLASS:
/*
@@ -2312,8 +2305,6 @@ static void blacklist_trtt(struct intel_engine_cs *engine)
static void pvc_whitelist_build(struct intel_engine_cs *engine)
{
- allow_read_ctx_timestamp(engine);
-
/* Wa_16014440446:pvc */
blacklist_trtt(engine);
}
@@ -2347,7 +2338,7 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
else if (IS_DG2(i915))
dg2_whitelist_build(engine);
else if (IS_XEHPSDV(i915))
- xehpsdv_whitelist_build(engine);
+ ; /* none needed */
else if (IS_DG1(i915))
dg1_whitelist_build(engine);
else if (GRAPHICS_VER(i915) == 12)