diff options
| author | Iwona Winiarska <[email protected]> | 2024-04-17 15:48:49 +0200 |
|---|---|---|
| committer | Iwona Winiarska <[email protected]> | 2024-06-17 15:18:29 +0200 |
| commit | aba59ce109deca2b9abeb9072ddca0ea8682bf5a (patch) | |
| tree | 83a8b6490330b7c5c5ccea40d3fc531caef21058 | |
| parent | a43b9ec091b1b1924ea18883a715e5aadba2543e (diff) | |
peci: aspeed: Clear clock_divider value before setting it
PECI clock divider is programmed on 10:8 bits of PECI Control register.
Before setting a new value, clear bits read from hardware.
Reviewed-by: Billy Tsai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Iwona Winiarska <[email protected]>
| -rw-r--r-- | drivers/peci/controller/peci-aspeed.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/peci/controller/peci-aspeed.c b/drivers/peci/controller/peci-aspeed.c index 7fdc25afcf2f..de7046e6b9c4 100644 --- a/drivers/peci/controller/peci-aspeed.c +++ b/drivers/peci/controller/peci-aspeed.c @@ -351,6 +351,7 @@ static int clk_aspeed_peci_set_rate(struct clk_hw *hw, unsigned long rate, clk_aspeed_peci_find_div_values(this_rate, &msg_timing, &clk_div_exp); val = readl(aspeed_peci->base + ASPEED_PECI_CTRL); + val &= ~ASPEED_PECI_CTRL_CLK_DIV_MASK; val |= FIELD_PREP(ASPEED_PECI_CTRL_CLK_DIV_MASK, clk_div_exp); writel(val, aspeed_peci->base + ASPEED_PECI_CTRL); |