diff options
| author | Philipp Zabel <[email protected]> | 2016-08-29 08:32:03 +0200 |
|---|---|---|
| committer | Philipp Zabel <[email protected]> | 2016-10-20 14:40:21 +0200 |
| commit | a92d81456c08ea6917a7630718837f0a01cbd0d0 (patch) | |
| tree | aed5d45b049d1509ee64d31c90ce0fa337c79349 | |
| parent | eae13c9337e2bba0f59b1723114e73be18499c5b (diff) | |
gpu: ipu-v3: initially clear all interrupts
If we want to stop resetting the IPU in the future, masking all
interrupts before registering the irq handlers will not be enough to
avoid spurious interrupts. We also have to clear them.
Signed-off-by: Philipp Zabel <[email protected]>
Acked-by: Liu Ying <[email protected]>
| -rw-r--r-- | drivers/gpu/ipu-v3/ipu-common.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c index b7d7bd6e3d60..97218af4fe75 100644 --- a/drivers/gpu/ipu-v3/ipu-common.c +++ b/drivers/gpu/ipu-v3/ipu-common.c @@ -1286,8 +1286,11 @@ static int ipu_irq_init(struct ipu_soc *ipu) return ret; } - for (i = 0; i < IPU_NUM_IRQS; i += 32) + /* Mask and clear all interrupts */ + for (i = 0; i < IPU_NUM_IRQS; i += 32) { ipu_cm_write(ipu, 0, IPU_INT_CTRL(i / 32)); + ipu_cm_write(ipu, ~unused[i / 32], IPU_INT_STAT(i / 32)); + } for (i = 0; i < IPU_NUM_IRQS; i += 32) { gc = irq_get_domain_generic_chip(ipu->domain, i); |