diff options
| author | Arun Siluvery <[email protected]> | 2016-01-21 21:43:51 +0000 |
|---|---|---|
| committer | Daniel Vetter <[email protected]> | 2016-01-25 16:48:35 +0100 |
| commit | a786d53a2cf14f2c7abb6731f530aef1a8a1086a (patch) | |
| tree | b679880cafc513f703c45b20760138521f4b722f | |
| parent | 2c8580e4e21c17011e78e7ac4e1fbab8b0d632bf (diff) | |
drm/i915/bxt: Add GEN8_L3SQCREG4 to HW whitelist
Required for WaDisableLSQCROPERFforOCL:bxt
According to WA database these are only applicable for BXT:A0 but since
A0 and A1 shares the same GT these are extended for A1 as well.
This register is added to HW whitelist to support WA required for future
enabling of pre-emptive command execution, WA implementation will be in
userspace and it cannot program this register if it is not on HW whitelist.
v2: explain purpose of changes (Chris)
Reviewed-by: Nick Hoath <[email protected]>
Signed-off-by: Arun Siluvery <[email protected]>
Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
Signed-off-by: Daniel Vetter <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index a99f8340fb47..12eb1e0f786b 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1136,10 +1136,15 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring) /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */ /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */ /* WaDisableObjectLevelPreemtionForInstanceId:bxt */ + /* WaDisableLSQCROPERFforOCL:bxt */ if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { ret = wa_ring_whitelist_reg(ring, GEN9_CS_DEBUG_MODE1); if (ret) return ret; + + ret = wa_ring_whitelist_reg(ring, GEN8_L3SQCREG4); + if (ret) + return ret; } return 0; |