diff options
| author | Paul Cercueil <[email protected]> | 2018-05-20 16:31:16 +0000 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2018-06-01 23:21:33 -0700 |
| commit | a6523b6fb8b54bd53b63c1ca171bed7d9dd3f68e (patch) | |
| tree | 80fb79603ed9d4062fac7b1835372761b6e497eb | |
| parent | 45ba63a29fd9b8a461110185e3abc5b4c90b806a (diff) | |
clk: ingenic: jz4770: Enable power of AHB1 bus after ungating VPU clock
This was broken before, because the AHB1 bus was enabled before the VPU
clock was ungated, while it must be done afterwards.
Signed-off-by: Paul Cercueil <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
| -rw-r--r-- | drivers/clk/ingenic/jz4770-cgu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c index a5ad69464e57..314f3143ca61 100644 --- a/drivers/clk/ingenic/jz4770-cgu.c +++ b/drivers/clk/ingenic/jz4770-cgu.c @@ -154,7 +154,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { "h1clk", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4770_CLK_PLL0, }, .div = { CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1 }, - .gate = { CGU_REG_LCR, 30 }, + .gate = { CGU_REG_CLKGR1, 7 }, }, [JZ4770_CLK_H2CLK] = { "h2clk", CGU_CLK_DIV, @@ -362,7 +362,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { [JZ4770_CLK_VPU] = { "vpu", CGU_CLK_GATE, .parents = { JZ4770_CLK_H1CLK, }, - .gate = { CGU_REG_CLKGR1, 7 }, + .gate = { CGU_REG_LCR, 30 }, }, [JZ4770_CLK_MMC0] = { "mmc0", CGU_CLK_GATE, |