diff options
| author | Stephane Eranian <[email protected]> | 2013-01-24 16:10:33 +0100 |
|---|---|---|
| committer | Arnaldo Carvalho de Melo <[email protected]> | 2013-04-01 12:16:49 -0300 |
| commit | a63fcab45273174e665e6a8c9fa1a79a9046d0d5 (patch) | |
| tree | 9e226f2d0b16af00e07762cef783c7cae2b27b15 | |
| parent | f20093eef5f7843a25adfc0512617d4b1ff1aa6e (diff) | |
perf/x86: Export PEBS load latency threshold register to sysfs
Make the PEBS Load Latency threshold register layout
and encoding visible to user level tools.
Signed-off-by: Stephane Eranian <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Ingo Molnar <[email protected]>
Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
| -rw-r--r-- | arch/x86/kernel/cpu/perf_event_intel.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index d5ea5a03cd37..ae6096b175b9 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -1781,6 +1781,8 @@ static void intel_pmu_flush_branch_stack(void) PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); +PMU_FORMAT_ATTR(ldlat, "config1:0-15"); + static struct attribute *intel_arch3_formats_attr[] = { &format_attr_event.attr, &format_attr_umask.attr, @@ -1791,6 +1793,7 @@ static struct attribute *intel_arch3_formats_attr[] = { &format_attr_cmask.attr, &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */ + &format_attr_ldlat.attr, /* PEBS load latency */ NULL, }; |