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authorAndre Przywara <[email protected]>2023-03-20 00:52:46 +0000
committerJernej Skrabec <[email protected]>2023-03-27 22:45:22 +0200
commita3eebcb61ffb9a26ca77a00ce80050cff0f0ecf3 (patch)
tree8b5321e847179550c3aaafe686bad18b4b6e77b3
parentcc1858614f5d99d87d4467079c25f6bdf434add9 (diff)
dts: add riscv include prefix link
The Allwinner D1/D1s SoCs (with a RISC-V core) use an (almost?) identical die as their R528/T113-s siblings with ARM Cortex-A7 cores. To allow sharing the basic SoC .dtsi files across those two architectures as well, introduce a symlink to the RISC-V DT directory. Signed-off-by: Andre Przywara <[email protected]> Reviewed-by: Conor Dooley <[email protected]> Acked-by: Palmer Dabbelt <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jernej Skrabec <[email protected]>
l---------scripts/dtc/include-prefixes/riscv1
1 files changed, 1 insertions, 0 deletions
diff --git a/scripts/dtc/include-prefixes/riscv b/scripts/dtc/include-prefixes/riscv
new file mode 120000
index 000000000000..202509418938
--- /dev/null
+++ b/scripts/dtc/include-prefixes/riscv
@@ -0,0 +1 @@
+../../../arch/riscv/boot/dts \ No newline at end of file