diff options
| author | Chanho Park <[email protected]> | 2021-10-18 21:42:09 +0900 |
|---|---|---|
| committer | Martin K. Petersen <[email protected]> | 2021-10-27 23:10:11 -0400 |
| commit | a271885ac6b2b5655d42eb8e13fdbf4b45a35d83 (patch) | |
| tree | b042c27538db103823ed370283b7b0ec368fcaf1 | |
| parent | 533b81d674452d180c5801290fd84a5c7ddeaaeb (diff) | |
scsi: ufs: ufs-exynos: Add EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR option
To skip exynos_ufs_config_phy_*_attr settings for exynos-ufs variant,
provide EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR as an opts flag.
For the ExynosAuto v9 SoC's controller, M-Phy timing setting is not
required and most of vendor-specific configuration will be performed in the
pre_link callback function.
Link: https://lore.kernel.org/r/[email protected]
Cc: Alim Akhtar <[email protected]>
Cc: Kiwoong Kim <[email protected]>
Cc: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Chanho Park <[email protected]>
Signed-off-by: Martin K. Petersen <[email protected]>
| -rw-r--r-- | drivers/scsi/ufs/ufs-exynos.c | 6 | ||||
| -rw-r--r-- | drivers/scsi/ufs/ufs-exynos.h | 1 |
2 files changed, 5 insertions, 2 deletions
diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c index b9257d72e9c8..2c15fde5c8d0 100644 --- a/drivers/scsi/ufs/ufs-exynos.c +++ b/drivers/scsi/ufs/ufs-exynos.c @@ -830,8 +830,10 @@ static int exynos_ufs_pre_link(struct ufs_hba *hba) /* m-phy */ exynos_ufs_phy_init(ufs); - exynos_ufs_config_phy_time_attr(ufs); - exynos_ufs_config_phy_cap_attr(ufs); + if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR)) { + exynos_ufs_config_phy_time_attr(ufs); + exynos_ufs_config_phy_cap_attr(ufs); + } exynos_ufs_setup_clocks(hba, true, PRE_CHANGE); diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h index 74f556d8a003..89955ae226dc 100644 --- a/drivers/scsi/ufs/ufs-exynos.h +++ b/drivers/scsi/ufs/ufs-exynos.h @@ -199,6 +199,7 @@ struct exynos_ufs { #define EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL BIT(2) #define EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX BIT(3) #define EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER BIT(4) +#define EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR BIT(5) }; #define for_each_ufs_rx_lane(ufs, i) \ |