diff options
| author | Sinan Kaya <[email protected]> | 2018-04-12 22:30:44 -0400 |
|---|---|---|
| committer | James Hogan <[email protected]> | 2018-04-14 00:46:53 +0100 |
| commit | a1cc7034e33d12dc17d13fbcd7d597d552889097 (patch) | |
| tree | b95a0cd926555f26ec83f127b2c3e76b7f0e86a8 | |
| parent | f6b7aeee8f167409195fbf1364d02988fecad1d0 (diff) | |
MIPS: io: Add barrier after register read in readX()
While a barrier is present in the writeX() functions before the register
write, a similar barrier is missing in the readX() functions after the
register read. This could allow memory accesses following readX() to
observe stale data.
Signed-off-by: Sinan Kaya <[email protected]>
Reported-by: Arnd Bergmann <[email protected]>
Cc: Ralf Baechle <[email protected]>
Cc: Paul Burton <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/19069/
[[email protected]: Tidy commit message]
Signed-off-by: James Hogan <[email protected]>
| -rw-r--r-- | arch/mips/include/asm/io.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index fd00ddafb425..a7d0b836f2f7 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -377,6 +377,8 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \ BUG(); \ } \ \ + /* prevent prefetching of coherent DMA data prematurely */ \ + rmb(); \ return pfx##ioswab##bwlq(__mem, __val); \ } |