diff options
| author | Robert Foss <[email protected]> | 2022-07-06 17:43:37 +0200 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2022-07-06 15:23:07 -0500 |
| commit | 9fd4887cdec6395a4ff447af8988bce61b707fb0 (patch) | |
| tree | 81c5cc5c6c022bdfdf646fc382b2a130b4aea0c5 | |
| parent | 1352b152880b84b843f3ee1bc1d0a133c0e1dd10 (diff) | |
arm64: dts: qcom: sm8350: Add DISPCC node
Add the dispcc clock-controller DT node for sm8350.
Signed-off-by: Robert Foss <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm8350.dtsi | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 6eb78d7ae8c5..bd82be765898 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,dispcc-sm8350.h> #include <dt-bindings/clock/qcom,gcc-sm8350.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/dma/qcom-gpi.h> @@ -2531,6 +2532,31 @@ }; }; + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8350-dispcc"; + reg = <0 0x0af00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + clock-names = "bi_tcxo", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + power-domains = <&rpmhpd SM8350_MMCX>; + power-domain-names = "mmcx"; + }; + adsp: remoteproc@17300000 { compatible = "qcom,sm8350-adsp-pas"; reg = <0 0x17300000 0 0x100>; |