diff options
| author | Chen-Yu Tsai <[email protected]> | 2022-09-27 12:11:20 +0200 |
|---|---|---|
| committer | Chen-Yu Tsai <[email protected]> | 2022-09-29 12:01:43 +0800 |
| commit | 9f94f545f258b15bfa6357eb62e1e307b712851e (patch) | |
| tree | 1ead490c56ac153b84852aa925c0ac2481ccb249 | |
| parent | 9ec105db6d13101627dc1f991904a3b07a32c998 (diff) | |
clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent
The only clock in the MT8183 MFGCFG block feeds the GPU. Propagate its
rate change requests to its parent, so that DVFS for the GPU can work
properly.
Fixes: acddfc2c261b ("clk: mediatek: Add MT8183 clock support")
Signed-off-by: Chen-Yu Tsai <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Chen-Yu Tsai <[email protected]>
| -rw-r--r-- | drivers/clk/mediatek/clk-mt8183-mfgcfg.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c index f578b393f41e..730c9ae5ea12 100644 --- a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c +++ b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c @@ -18,9 +18,9 @@ static const struct mtk_gate_regs mfg_cg_regs = { .sta_ofs = 0x0, }; -#define GATE_MFG(_id, _name, _parent, _shift) \ - GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, \ - &mtk_clk_gate_ops_setclr) +#define GATE_MFG(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_SET_RATE_PARENT) static const struct mtk_gate mfg_clks[] = { GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0) |