diff options
| author | Stephen Boyd <[email protected]> | 2022-11-22 16:51:29 -0800 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2022-11-22 16:51:29 -0800 |
| commit | 9f8e30559b0425d4372c643aef4ddea547a3c1ac (patch) | |
| tree | 58a85c88f76be820372ef996b663cf1b55e5d201 | |
| parent | 9abf2313adc1ca1b6180c508c25f22f9395cc780 (diff) | |
| parent | f64603c9729af406167cb9beb66687b1abc4196e (diff) | |
Merge tag 'sunxi-clk-for-6.2-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner
Pull Allwinner clk driver updates from Jernej Skrabec:
- Fixed header guard for V3S clocks
- Add IR module clock for f1c100s
* tag 'sunxi-clk-for-6.2-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: f1c100s: Add IR mod clock
clk: sunxi-ng: v3s: Correct the header guard of ccu-sun8i-v3s.h
| -rw-r--r-- | drivers/clk/sunxi-ng/ccu-sun8i-v3s.h | 6 | ||||
| -rw-r--r-- | drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c | 11 | ||||
| -rw-r--r-- | drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h | 2 | ||||
| -rw-r--r-- | include/dt-bindings/clock/suniv-ccu-f1c100s.h | 2 |
4 files changed, 16 insertions, 5 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h index 108eeeedcbf7..345cdbbab362 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h @@ -6,8 +6,8 @@ * Copyright (c) 2016 Maxime Ripard <[email protected]> */ -#ifndef _CCU_SUN8I_H3_H_ -#define _CCU_SUN8I_H3_H_ +#ifndef _CCU_SUN8I_V3S_H_ +#define _CCU_SUN8I_V3S_H_ #include <dt-bindings/clock/sun8i-v3s-ccu.h> #include <dt-bindings/reset/sun8i-v3s-ccu.h> @@ -51,4 +51,4 @@ #define CLK_PLL_DDR1 74 -#endif /* _CCU_SUN8I_H3_H_ */ +#endif /* _CCU_SUN8I_V3S_H_ */ diff --git a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c index ed097c4f780f..0d5b60b123b7 100644 --- a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c +++ b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c @@ -239,7 +239,14 @@ static SUNXI_CCU_MUX_WITH_GATE(i2s_clk, "i2s", i2s_spdif_parents, static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_spdif_parents, 0x0b4, 16, 2, BIT(31), 0); -/* The BSP header file has a CIR_CFG, but no mod clock uses this definition */ +static const char * const ir_parents[] = { "osc32k", "osc24M" }; +static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir", + ir_parents, 0x0b8, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 0x0cc, BIT(1), 0); @@ -355,6 +362,7 @@ static struct ccu_common *suniv_ccu_clks[] = { &mmc1_output_clk.common, &i2s_clk.common, &spdif_clk.common, + &ir_clk.common, &usb_phy0_clk.common, &dram_ve_clk.common, &dram_csi_clk.common, @@ -446,6 +454,7 @@ static struct clk_hw_onecell_data suniv_hw_clks = { [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, [CLK_I2S] = &i2s_clk.common.hw, [CLK_SPDIF] = &spdif_clk.common.hw, + [CLK_IR] = &ir_clk.common.hw, [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, [CLK_DRAM_VE] = &dram_ve_clk.common.hw, [CLK_DRAM_CSI] = &dram_csi_clk.common.hw, diff --git a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h index b22484f1bb9a..d56a4316289d 100644 --- a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h +++ b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h @@ -29,6 +29,6 @@ /* All bus gates, DRAM gates and mod clocks are exported */ -#define CLK_NUMBER (CLK_AVS + 1) +#define CLK_NUMBER (CLK_IR + 1) #endif /* _CCU_SUNIV_F1C100S_H_ */ diff --git a/include/dt-bindings/clock/suniv-ccu-f1c100s.h b/include/dt-bindings/clock/suniv-ccu-f1c100s.h index f5ac155c9c70..d7570765f424 100644 --- a/include/dt-bindings/clock/suniv-ccu-f1c100s.h +++ b/include/dt-bindings/clock/suniv-ccu-f1c100s.h @@ -67,4 +67,6 @@ #define CLK_CODEC 65 #define CLK_AVS 66 +#define CLK_IR 67 + #endif |