diff options
| author | AngeloGioacchino Del Regno <[email protected]> | 2023-06-22 11:27:39 +0200 |
|---|---|---|
| committer | Will Deacon <[email protected]> | 2023-08-09 12:44:28 +0100 |
| commit | 9f3fef23d9b5a858a6e6d5f478bb1b6b76265e76 (patch) | |
| tree | 4293d384acdfd438f79bb9e527c7528bdd19cfcf | |
| parent | fcf226f1f7083cba76af47bf8dd764b68b149cd2 (diff) | |
iommu/qcom: Disable and reset context bank before programming
Writing the new TTBRs, TCRs and MAIRs on a previously enabled
context bank may trigger a context fault, resulting in firmware
driven AP resets: change the domain initialization programming
sequence to disable the context bank(s) and to also clear the
related fault address (CB_FAR) and fault status (CB_FSR)
registers before writing new values to TTBR0/1, TCR/TCR2, MAIR0/1.
Fixes: 0ae349a0f33f ("iommu/qcom: Add qcom_iommu")
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Will Deacon <[email protected]>
| -rw-r--r-- | drivers/iommu/arm/arm-smmu/qcom_iommu.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c index 8c717bc2d9fb..a352859edea8 100644 --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c @@ -273,6 +273,13 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, ctx->secure_init = true; } + /* Disable context bank before programming */ + iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0); + + /* Clear context bank fault address fault status registers */ + iommu_writel(ctx, ARM_SMMU_CB_FAR, 0); + iommu_writel(ctx, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT); + /* TTBRs */ iommu_writeq(ctx, ARM_SMMU_CB_TTBR0, pgtbl_cfg.arm_lpae_s1_cfg.ttbr | |