diff options
| author | Zev Weiss <[email protected]> | 2023-02-23 16:04:00 -0800 |
|---|---|---|
| committer | Joel Stanley <[email protected]> | 2023-03-06 11:23:18 +1030 |
| commit | 9dedb724446913ea7b1591b4b3d2e3e909090980 (patch) | |
| tree | 5be924af6f2ba94c73c1bdedef165de90b324b61 | |
| parent | 8bc5ae1d2b207b855010591adeace94f9ec4caf2 (diff) | |
ARM: dts: aspeed: asrock: Correct firmware flash SPI clocks
While I'm not aware of any problems that have occurred running these
at 100 MHz, the official word from ASRock is that 50 MHz is the
correct speed to use, so let's be safe and use that instead.
Signed-off-by: Zev Weiss <[email protected]>
Cc: [email protected]
Fixes: 2b81613ce417 ("ARM: dts: aspeed: Add ASRock E3C246D4I BMC")
Fixes: a9a3d60b937a ("ARM: dts: aspeed: Add ASRock ROMED8HM3 BMC")
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Joel Stanley <[email protected]>
| -rw-r--r-- | arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts index 67a75aeafc2b..c4b2efbfdf56 100644 --- a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts +++ b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts @@ -63,7 +63,7 @@ status = "okay"; m25p,fast-read; label = "bmc"; - spi-max-frequency = <100000000>; /* 100 MHz */ + spi-max-frequency = <50000000>; /* 50 MHz */ #include "openbmc-flash-layout.dtsi" }; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts index 00efe1a93a69..4554abf0c7cd 100644 --- a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts +++ b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts @@ -51,7 +51,7 @@ status = "okay"; m25p,fast-read; label = "bmc"; - spi-max-frequency = <100000000>; /* 100 MHz */ + spi-max-frequency = <50000000>; /* 50 MHz */ #include "openbmc-flash-layout-64.dtsi" }; }; |