diff options
| author | Pierre-Louis Bossart <[email protected]> | 2022-04-14 13:48:13 -0500 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2022-04-19 12:03:42 +0100 |
| commit | 9d201b69d04b89369240c1a7e279fda85cc94720 (patch) | |
| tree | b1803033e702cb1de178b777862c56f077f85191 | |
| parent | 406fed8092d96e3cd565d6041dc381d630039fe0 (diff) | |
ASoC: SOF: Intel: hda: use BIT() macros for consistency
BIT() macros should be used for all ADSPIC/IS registers.
Signed-off-by: Pierre-Louis Bossart <[email protected]>
Reviewed-by: Péter Ujfalusi <[email protected]>
Reviewed-by: Ranjani Sridharan <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
| -rw-r--r-- | sound/soc/sof/intel/hda.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/sound/soc/sof/intel/hda.h b/sound/soc/sof/intel/hda.h index cc55439ab187..f7a93012b811 100644 --- a/sound/soc/sof/intel/hda.h +++ b/sound/soc/sof/intel/hda.h @@ -223,8 +223,8 @@ #define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */ #define HDA_DSP_REG_POLL_RETRY_COUNT 50 -#define HDA_DSP_ADSPIC_IPC 1 -#define HDA_DSP_ADSPIS_IPC 1 +#define HDA_DSP_ADSPIC_IPC BIT(0) +#define HDA_DSP_ADSPIS_IPC BIT(0) /* Intel HD Audio General DSP Registers */ #define HDA_DSP_GEN_BASE 0x0 @@ -268,8 +268,8 @@ /* HIPCTE */ #define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF -#define HDA_DSP_ADSPIC_CL_DMA 0x2 -#define HDA_DSP_ADSPIS_CL_DMA 0x2 +#define HDA_DSP_ADSPIC_CL_DMA BIT(1) +#define HDA_DSP_ADSPIS_CL_DMA BIT(1) /* Delay before scheduling D0i3 entry */ #define BXT_D0I3_DELAY 5000 |