diff options
| author | Amelie Delaunay <[email protected]> | 2020-08-10 09:12:36 +0200 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2020-08-10 19:46:43 +0100 |
| commit | 9cc61973bf9385b19ff5dda4a2a7e265fcba85e4 (patch) | |
| tree | fa182a40d677509123a611bf0c2ece2aefb4d313 | |
| parent | 3373e9004acc0603242622b4378c64bc01d21b5f (diff) | |
spi: stm32: fix stm32_spi_prepare_mbr in case of odd clk_rate
Fix spi->clk_rate when it is odd to the nearest lowest even value because
minimum SPI divider is 2.
Signed-off-by: Amelie Delaunay <[email protected]>
Signed-off-by: Alain Volmat <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
| -rw-r--r-- | drivers/spi/spi-stm32.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c index e5450233f3f8..571dea72bf7e 100644 --- a/drivers/spi/spi-stm32.c +++ b/drivers/spi/spi-stm32.c @@ -441,7 +441,8 @@ static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz, { u32 div, mbrdiv; - div = DIV_ROUND_UP(spi->clk_rate, speed_hz); + /* Ensure spi->clk_rate is even */ + div = DIV_ROUND_UP(spi->clk_rate & ~0x1, speed_hz); /* * SPI framework set xfer->speed_hz to master->max_speed_hz if |